In conventional nonvolatile semiconductor memory devices (memory), elements are integrated in a two-dimensional plane on a silicon substrate. Although the dimensions of one element are reduced (downscaled) to increase the storage capacity of the memory, such downscaling in recent years has become difficult in regard to both cost and technology.
On the other hand, although many ideas for three-dimensional memory, etc., have been proposed, three-dimensional devices generally require processes including at least three lithography processes for each layer. Therefore, costs cannot be reduced even when three-dimensional; and instead, stacking four or more layers undesirably leads to cost increases.
Conversely, collectively patterned three-dimensionally stacked memory cells have been proposed (for example, refer to JP-A 2007-266143 (Kokai)). According to such a method, it is possible to collectively form a stacked memory regardless of the number of stacks. Therefore, it is possible to suppress cost increases.
In such a collectively patterned three-dimensionally stacked memory, a stacked unit is formed on a silicon substrate by alternately stacking insulating films with electrode films forming word lines, and then collectively making through-holes in the stacked unit. Then, for example, a charge storage layer is provided on the side faces of the through-holes; and silicon pillars are provided by filling silicon thereinto. A tunneling insulating film is provided between the charge storage layer and the silicon pillars; and a blocking insulating film is provided between the charge storage layer and the electrode films. Thereby, a memory cell is formed at the intersection between the silicon pillars and each of the electrode films.
Further, two of the through-holes may be connected at the bottoms to form a silicon pillar having a U-shaped configuration. In other words, a memory film including a charge storage layer is formed on the side wall of the through-hole having the U-shaped configuration; and silicon is filled thereinto. Thereby, a memory string made of a silicon pillar having a U-shaped structure can be formed.
In a three-dimensionally stacked memory having such a structure, it is difficult to sufficiently perform erasing operations. Moreover, applying excessive erasing voltage to sufficiently perform the erasing may cause the reliability to deteriorate. For example, because electron injection (back-tunneling) occurs from the blocking oxide film side when the erasing operation is performed, not only is it impossible to bring the memory cell to or below the desired threshold value, but also hot holes created when the electrons reach the channel side are re-injected into the tunneling insulating film; and the reliability of the tunneling insulating film deteriorates.
Thus, there exists a great need to suppress the back-tunneling during the erasing operation of a nonvolatile semiconductor memory device having a collectively patterned three-dimensionally stacked structure to thereby improve the erasing characteristics and increase the reliability.